1. Technical Field
The present invention relates to a circuit and method for controlling an internal voltage of a semiconductor memory apparatus, and more particularly, to a circuit and method for controlling an internal voltage of a semiconductor memory apparatus which are capable of reducing a leakage current by sinking the internal voltage of a level shifter to a ground voltage when the semiconductor memory apparatus is in a deep power down mode.
2. Related Art
In general, semiconductor memory apparatuses, such as DRAMs (dynamic random access memories), operate in an active state and in a stand-by state. When the semiconductor memory apparatus is in the active state, circuits inside a chip output data or receive data. On the other hand, when the semiconductor memory apparatus is in the stand-by state, in order to reduce the power consumption of the chip to a minimum, a current is supplied to only the circuits that allow the semiconductor memory apparatus to be transferred to the active state. However, when the semiconductor memory apparatus is kept in the stand-by state for a long time, a current continuously flows through the circuit keeping it enabled, in order to allow the semiconductor memory apparatus to enter the active state, resulting in unnecessary power consumption.
Therefore, in the related art, a method has been used of transferring a semiconductor memory apparatus to a deep power down mode in which, in order to reduce the amount of current flowing in the stand-by state, almost all the current paths of a chip are blocked to reduce a stand-by current to a minimum. In addition, in the deep power down mode, in order to prevent the semiconductor memory apparatus from being unnecessarily operated due to the current remaining in the internal circuits of a chip, all the voltages of the internal circuits, such as an elevated voltage, a core voltage, a bit-line pre-charge voltage, and a substrate bias voltage, are sunk to a ground voltage. As described above, in the deep power down mode, except for a command for instructing the start and end of the deep power down mode, the levels of all data stored in, for example, a memory cell and a register are sunk to the ground voltage.
A level shifter is used between power supplies having different voltage levels in the semiconductor memory apparatus. In particular, since the elevated voltage is the highest voltage of the voltages used in the semiconductor memory apparatus, a level shifter is typically used in a circuit having an external voltage source and an elevated voltage source connected to each other. Therefore, a description will be made below of an example in which the elevated voltage is used as an internal voltage of the semiconductor memory apparatus.
FIG. 1 is a diagram illustrating a level shifter according to the related art.
More specifically, FIG. 1 shows a level shifter 10 for converting the external voltage VDD into the elevated voltage VPP in response to the input of a control signal ctrl.
The level shifter 10 is composed of a differential amplifier which uses the elevated voltage VPP and a ground voltage VSS as a power supply voltage and includes four transistors TR1 to TR4 operated in response to the input of the external voltage VDD. In addition, a first inverter IV1 having the elevated voltage VPP applied thereto is provided at an output end of the level shifter 10.
The level shifter 10 operates in response to the input of the control signal ctrl. When the control signal ctrl changes to an enable state and is transmitted to the level shifter 10 as a high-level signal, the fourth transistor TR4 of the level shifter 10 is turned on. At that time, the third transistor TR3 has already been turned on by the external voltage VDD. Since a high-level voltage is applied to a node N1 by the control signal ctrl, a high-level voltage is also applied to the node N2. Therefore, the second transistor TR2 is turned off and the fourth transistor TR4 is turned on, which causes the voltage level of a node N3 to be lowered to the ground voltage VSS. Thereafter, the low-level voltage of the node N3 causes the first transistor TR1 to be turned on, so that the elevated voltage VPP is applied to the node N2.
The low-level voltage applied to the node N3 is inverted into a high-level voltage by the first inverter IV1, and the inverted voltage is output as a signal having the level of the elevated voltage VPP.
At that time, since the voltage level of the node N2 is high, the second transistor TR2 is turned off. Therefore, even when the semiconductor memory level is transferred to the deep power down mode and the generation of the elevated voltage VPP stops, the elevated voltage VPP of the level shifter 10 is not sunk to the ground voltage VSS.
The level shifter 10 does not include a circuit for sinking the elevated voltage VPP to the ground voltage VSS. Level shifters used for various other parts of the semiconductor memory apparatus as well as the level shifter 10 hold a predetermined level of voltage for a long time in the deep power down mode. In the deep power down mode, a leakage current is generated by the circuits whose levels are not immediately sunk to the ground voltage VSS in the deep power down mode.